AI accelerator specs

Selected specs reviewed 2026-10-15. Row is the MI455X, whose dense rates AMD publishes directly (5.0 PF BF16, 20.1 PF FP8, 40.3 PF MXFP4); 23.3 TB/s HBM4 bandwidth and 2,500 W maximum board power.

Selected specs reviewed 2026-10-15. Rubin GPU column: 19.2 TB/s and NVLink 6 at 3 TB/s (HGX and preliminary DGX Rubin NVL8 pages still imply 22 and 3.6 TB/s). 1,800 W is the datasheet's NVL4 benchmark power; NVIDIA states no process node.

Selected specs reviewed 2026-10-15. Peak-specification table: 5,072 TFLOPS FP8, 10,145 TFLOPS FP4, 750 W. BF16 (1,268 TFLOPS) is a vector-unit rate, so tf16 stays empty.

Selected specs reviewed 2026-10-15. 671 TFLOPS dense BF16; 2,517 TFLOPS MXFP8 and MXFP4. Dense BF16 cannot be inferred by halving FP8; AWS publishes no per-chip power.

Selected specs reviewed 2026-10-15. Current TPU7x table (7,380 GB/s shown as 7.38 TB/s); GA since March 31, 2026. No FP4 rate or per-chip power is published.

Selected specs reviewed 2026-10-15. Use explicit dense BF16/OCP-FP8 and MXFP4 rates, not the adjacent sparse headline values.

Selected specs reviewed 2026-10-15. Current HGX column specifies 270 GB, 7.7 TB/s and 1,100 W; older reference tables list 288 GB. Dense FP4 is 108 PF/system ÷ 8 (the per-GPU figure is rounded to 14 PF in the PDF).

Selected specs reviewed 2026-10-15. Datasheet's individual-GPU column for GB200 NVL72: its sparse FP4/FP8/BF16 figures (20/10/5 PF) halved, as its footnote directs, to 10/5/2.5 PF dense; the rack page's totals divide to the same. 186 GB HBM3E at 8 TB/s and a TDP configurable up to 1,200 W per GPU.

Selected specs reviewed 2026-10-15. Dense FP32-accumulate tensor rates: BF16 209.5 TFLOPS, FP8 419 TFLOPS, FP4 1,676 TFLOPS; process TSMC 4N. The whitepaper's 2× FP16-accumulate rates are not comparable with data-center specifications.

Selected specs reviewed 2026-10-15. HGX B200 column: 7.7 TB/s per GPU (62 TB/s per board) replaces 8 TB/s, which DGX B200 pages still list. Per-GPU rates are derived from the eight-GPU table.

Selected specs reviewed 2026-10-15. Dense rates, 256 GB HBM3E and 6 TB/s confirmed.

Selected specs reviewed 2026-10-15. Dense compute and per-chip memory/interconnect; the 500 W board power remains a secondary estimate.

Selected specs reviewed 2026-10-15. Per-chip architecture comparison; FP8 throughput is explicitly listed, not inferred from BF16.

Selected specs reviewed 2026-10-15. Intel's July 2025 paper gives 1,678 TFLOPS BF16/FP8 MME at 900 W; its 2024 Hot Chips deck said 1,835.

Selected specs reviewed 2026-10-15. SXM column; sparse tensor figures divided by two, with existing whole-TFLOPS rounding retained.

Selected specs reviewed 2026-10-15. Dense rates confirmed; the datasheet's more precise 1,307.4/2,614.9 TFLOPS round to the table values.

Selected specs reviewed 2026-10-15. Per-chip table; FP8 runs at the BF16 rate and capacity is specified in GiB.

Selected specs reviewed 2026-10-15. Dense tensor rates are the unstarred figures (BF16 362.05, FP8 733 TFLOPS); the starred sparse ones are excluded, and no FP4 format is listed. 48 GB GDDR6 at 864 GB/s, 350 W, PCIe Gen4 x16 without NVLink. The page states no process node.

Selected specs reviewed 2026-10-15. 197 TFLOPS BF16 and 393 INT8 TOPS per chip; no FP8, FP4 or power figure is published. 0.82 TB/s follows Google's Trillium comparison; the v5e table's 800 GiBps would read 0.86.

Selected specs reviewed 2026-10-15. SXM column; sparse tensor figures divided by two, with existing whole-TFLOPS rounding retained.

Selected specs reviewed 2026-10-15. Dense FP32-accumulate tensor rates: BF16 165.2 TFLOPS, FP8 330.3 TFLOPS; no FP4 tensor format. The whitepaper's 2× FP16-accumulate rates are not comparable with data-center specifications.

Selected specs reviewed 2026-10-15. 80GB SXM column; process TSMC N7.

Selected specs reviewed 2026-10-15. SXM2 column; FP16 tensor only (no BF16, FP8 or FP4).